Simple Divide by 2 Clock Generator
System-on-chip designs frequently require multiple clock domains operating at integer fractions of a master oscillator. The fundamental building block for all even clock dividers is a circuit that produces an output toggling at exactly half the frequency of the input clock.
The circuit receives an input clock clk and an active-high reset rst. On every positive edge of clk, the output div_clk must update according to the following state table:
| rst | div_clk (current) | div_clk (next) | |-------|---------------------|------------------| | 1 | 0 | 0 | | 1 | 1 | 0 | | 0 | 0 | 1 | | 0 | 1 | 0 |
Constraints
- Implement the design using exactly one D flip-flop and one inverter.
- Do not use any other logic gates or sequential elements.
- Wire the D flip-flop to trigger on the positive edge of
clk.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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