Synchronous Divide by 4 Clock Generator
Lower frequency domains in digital ASICs require clean, edge-aligned signals to prevent timing violations. A synchronous clock divider generates a slower clock while maintaining strict phase alignment with the root clock tree.
Implement a synchronous divide-by-4 circuit. The output clk_div4 must toggle at one-fourth the frequency of the main system clock. A synchronous, active-high reset initializes the circuit state to zero. The sequence below demonstrates the expected cycle-by-cycle output behavior.
| reset | Cycle | clk_div4 | |---------|-------|------------| | 1 | 0 | 0 | | 0 | 1 | 0 | | 0 | 2 | 1 | | 0 | 3 | 1 | | 0 | 4 | 0 | | 0 | 5 | 0 |
Constraints
- All flip-flops must be clocked directly by the primary clock signal.
- Do not route the output of one flip-flop into the clock input of another.
- Implement the next-state logic using only combinational gates.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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