SIPO: Bit-Reversed Output Debug
A 4-bit Serial-In Parallel-Out (SIPO) shift register converts a serial data stream into a parallel word for external bus interfacing.
Expected behavior:
Data enters on the Sin pin and shifts through the register on each rising edge of CLK. After four clock cycles, the parallel output OUT3, OUT2, OUT1, OUT0 should match the 4-bit sequence received. The first bit received becomes the most significant bit OUT3.
Simulation shows that after shifting in the sequence 1, 0, 1, 1, the expected parallel output is OUT3=1, OUT2=0, OUT1=1, OUT0=1. The test observes an actual output of OUT3=1, OUT2=1, OUT1=0, OUT0=1. The parallel output data is corrupted. Inspect the circuit and correct the fault.
Constraints
- Maintain the four D-flip-flop chain for the core shift register.
- Ensure the output bus reflects the correct chronological order of the serial input.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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