SIPO: One Flip-Flop D Input Floating Debug
A 4-bit Serial-In Parallel-Out (SIPO) shift register converts serial data streams into parallel words for parallel bus interfaces.
Expected behavior:
On every rising edge of the clock, the serial input DataIn shifts into Q0. Simultaneously, Q0 shifts to Q1, Q1 shifts to Q2, and Q2 shifts to Q3.
When shifting in the data sequence 1, 0, 1, 1 starting from an all-zero state, the expected parallel output Q[3:0] sequence is 0001, 0010, 0101, and 1011.
Simulation shows incorrect parallel output words. During the sequence above, the observed outputs transition through 0001, 0010, 0001, and 1011. The bit at Q2 remains stuck at 0 across all clock cycles instead of receiving the shifted data. Inspect the circuit and correct the fault.
Constraints
- Do not add any new logic gates or flip-flops to the circuit.
- You must fix the routing of the existing components.
- The circuit must correctly shift data through all four stages.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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