SIPO with Start Bit Detection
Serial protocols use start bits to synchronize frames across asynchronous clock domains. Without start bit detection, a receiving shift register continuously captures misaligned garbage data during idle periods.
The idle state of the D_serial line is HIGH (1). A start bit is indicated by a single clock cycle where D_serial drops to LOW (0). When the start bit is detected, the circuit must shift the next 8 bits of D_serial into an 8-bit output register Q_parallel over the subsequent 8 clock cycles. The data is shifted in MSB-first.
The shift register must output its current internal state continuously on Q_parallel. Once all 8 bits are captured, the circuit must assert valid HIGH for exactly one clock cycle and immediately return to waiting for the next start bit. The start bit itself is not part of the 8-bit data payload.
Constraints
- Implement using standard logic gates, D flip-flops, and standard counters.
rstis active-high and synchronous.Q_parallelmust continuously reflect the internal shift register state.- The circuit must ignore
D_serialtransitions while actively shifting an 8-bit frame.
Topics
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