SIPO: MSB-First vs. LSB-First
Hardware communication protocols like SPI and UART transmit data sequentially over a single wire, but they disagree on bit ordering. A receiver wired for the wrong bit order will silently produce byte-reversed data.
Construct two 4-bit Serial-In Parallel-Out (SIPO) shift registers that process the same serial input sin. The Q_msb output must capture the stream MSB-first, meaning the first received bit shifts into the most significant position. The Q_lsb output must capture the stream LSB-first, meaning the first received bit shifts into the least significant position. Both registers update on the rising edge of the implied clock and clear to zero when rst is high.
| Cycle | rst | sin | Q_msb | Q_lsb | |-------|-------|-------|---------|---------| | 0 | 1 | X | 0000 | 0000 | | 1 | 0 | 1 | 0001 | 1000 | | 2 | 0 | 0 | 0010 | 0100 | | 3 | 0 | 1 | 0101 | 1010 | | 4 | 0 | 1 | 1011 | 1101 |
Constraints
- Use exactly eight D flip-flops to store the state for both 4-bit outputs.
- Route the serial input
sinto the lowest index flip-flop for the MSB-first register. - Route the serial input
sinto the highest index flip-flop for the LSB-first register. - Clear all register bits to zero synchronously when
rstis high.
Topics
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