8-Bit SIPO with Strobe-Gated Output Register
Serial data receivers require double buffering to prevent downstream logic from reading intermediate states during shifting. An output register isolates the internal shift register state, updating the visible parallel output only when a complete byte is ready.
The circuit receives a serial data stream on din. On every clock cycle, data shifts into an internal 8-bit shift register: the newest bit enters at position 0, and existing bits shift towards position 7. A separate 8-bit parallel register drives the output dout. When strobe is 1, this output register captures the current 8-bit state of the shift register. When strobe is 0, dout retains its previous value. The internal shift register must continue to shift in din regardless of the strobe signal.
Constraints
- Implement an 8-bit shift register and a separate 8-bit output register.
- The output
doutmust update only whenstrobeis 1. - The shift register must shift continuously on every clock cycle.
Topics
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