4-Bit SIPO: Parallel Output at Each Clock Cycle
A 4-bit serial-in, parallel-out (SIPO) shift register captures the serial input SIN into Q3 and shifts existing bits rightward (Q3→Q2→Q1→Q0) on every positive edge of CLK.
Six signals are involved: CLK (clock, period 2), SIN (serial input), and Q3, Q2, Q1, Q0 (parallel outputs, all initially 0).
Trace the four output signals Q3, Q2, Q1, and Q0 across all 12 time steps.
Constraints
- All flip-flops in the shift register update simultaneously on the positive clock edge.
- The parallel output lines hold partially shifted data during intermediate cycles.
- A full 4-bit frame is only completely valid on the outputs after 4 consecutive clock cycles.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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