4-Bit SIPO: Construction from SISO
Serial communication protocols like SPI or UART require converting sequential data streams into parallel words for microprocessor consumption. The Serial-In Parallel-Out (SIPO) register acts as this data deserializer by exposing the internal state of a shift register.
A SIPO is structurally identical to a Serial-In Serial-Out (SISO) register. The only distinction is that every intermediate flip-flop output is routed to an external parallel pin. On every rising edge of clk, the value at D is sampled into Q0. Simultaneously, the previous value of Q0 shifts to Q1, Q1 shifts to Q2, and Q2 shifts to Q3.
| clk edge | Q0 | Q1 | Q2 | Q3 | |------------|------|------|------|------| | Rising | D | Q0 | Q1 | Q2 |
Constraints
- Use exactly four D flip-flops.
- All flip-flops must share the same
clksignal. - Route the output of each flip-flop to both the next stage and its corresponding parallel output pin.
- Do not use pre-packaged shift register macros.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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