SISO: Recirculating Register Waveform Verification
A 4-bit recirculating shift register shifts right and feeds its least significant bit (Q0) back into its most significant bit (Q3) on every positive clock edge when LOAD is LOW.
Three signals are shown: CLK (positive-edge-triggered clock, period 2), LOAD (active-HIGH synchronous load), and Q3 (output, initially 0). When LOAD is HIGH at a rising clock edge, the register synchronously loads the state Q3 Q2 Q1 Q0 = 0110.
Trace Q3 across all 16 time steps to verify its period-4 repetition pattern.
Constraints
Q3updates only on the LOW-to-HIGH transition ofCLK.- Synchronous load takes priority over the shift operation.
- The register shifts right, meaning the value of
Q0from the previous cycle becomes the new value ofQ3.
Topics
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