SR NAND Latch: Simultaneous Forbidden-State Release Race
An active-low SR NAND latch sets Q to 1 when S_bar is 0, resets Q to 0 when R_bar is 0, and holds its state when both inputs are 1. Three signals are shown: S_bar (active-low set input), R_bar (active-low reset input), and Q (output, initially 0). Trace the value of Q across all 8 time steps, paying close attention to simultaneous input transitions.
Constraints
- The output
Qevaluates to 1 during the forbidden state where both active-low inputs are 0. - Use the character "X" for any time step where the output becomes indeterminate due to a race condition.
- A valid asynchronous reset or set overrides an indeterminate state.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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