SR NAND Latch: Forbidden State
An active-low SR NAND latch sets Q to 1 when S_bar is 0, resets Q to 0 when R_bar is 0, and holds its state when both inputs are 1. Four signals are shown: S_bar (set input), R_bar (reset input), Q (output), and Q_bar (inverted output). The initial state is Q = 0 and Q_bar = 1. Trace both Q and Q_bar across all 8 time steps. Pay special attention to the forbidden state and the subsequent release transitions.
Constraints
- Evaluate both NAND gates simultaneously at each time step.
- Use "X" to represent genuinely indeterminate states or race conditions.
- Do not assume
QandQ_barwill always be exact opposites.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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