SR NAND Latch Stuck Forbidden State Debug
An active-low SR NAND latch provides basic state retention in digital systems by storing a single bit of data.
Expected behavior:
| S_bar | R_bar | State Action | Q | Q_bar | |---------|---------|--------------|-----|---------| | 0 | 1 | Set | 1 | 0 | | 1 | 0 | Reset | 0 | 1 | | 1 | 1 | Hold | Retains previous state |
Simulation shows Q = 0 and Q_bar = 0 continuously for all input combinations. The latch fails to set or reset, and the outputs remain locked at a logic low regardless of the input vectors.
Inspect the circuit and correct the fault.
Constraints
- Do not alter the input or output port names.
- The final circuit must use a cross-coupled NAND gate topology.
- Ensure no nets are unintentionally shorted to ground or to each other.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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