Gated SR Latch: 4-NAND Construction
Transparent latches form the foundation of master-slave flip-flops and clock-gated memory arrays. Merging the enable logic directly into the cross-coupled storage element reduces gate count and propagation delay compared to using a discrete AND-gate enable layer.
Implement a gated SR latch using active-high inputs. When EN is high, the latch responds to the S and R signals. When EN is low, the latch holds its previous state regardless of the inputs.
| EN | S | R | Q | Qn | |------|-----|-----|-----|------| | 0 | 0 | 0 | Q_prev | Qn_prev | | 0 | 1 | 0 | Q_prev | Qn_prev | | 0 | 0 | 1 | Q_prev | Qn_prev | | 0 | 1 | 1 | Q_prev | Qn_prev | | 1 | 0 | 0 | Q_prev | Qn_prev | | 1 | 1 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | 1 |
*Note: The input condition where EN, S, and R are all 1 is considered invalid for standard SR latch operation and will not be tested.*
Constraints
- Use exactly 4 NAND gates.
- Do not use separate AND, OR, or NOT gates.
- Do not use built-in latch or flip-flop primitives.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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