Gated SR Latch: Transparency Window Trace

EasyLogic CircuitTiming Diagram

A gated SR latch passes the state of inputs S and R to output Q when enable EN is HIGH, and holds its current value when EN is LOW.

Four signals are shown: EN (enable input), S (set input), R (reset input) and Q (output, initially 0).

Trace Q across all 10 time steps.

Constraints

sequentialtiminglatchestransparency

Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

EasyLogic CircuitTiming Diagram

A gated SR latch passes the state of inputs S and R to output Q when enable EN is HIGH, and holds its current value when EN is LOW.

Four signals are shown: EN (enable input), S (set input), R (reset input) and Q (output, initially 0).

Trace Q across all 10 time steps.

sequentialtiminglatchestransparency

Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.