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Codiode/Problems/Sequential Logic

Gated SR Latch: Glitch Propagation During Enable Window

MediumLogic CircuitTiming Diagram

A gated SR latch updates its output based on the S and R inputs while the enable signal (EN) is HIGH, and holds its current state when EN is LOW.

Four signals are shown: EN (enable control), S (set input), R (reset input), and Q (output, initially 0).

Trace Q across all 14 time steps to determine how the latch captures or ignores transient input pulses based on the enable window.

Constraints

  • The S and R inputs will never be HIGH at the same time.
  • The latch is strictly level-sensitive and responds continuously to inputs during the transparent phase.

Topics

HazardsLatchesSequential LogicGlitches

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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

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