Gated SR Latch: Forbidden State During Enable Window
A gated SR latch updates its state from inputs S and R when EN is HIGH and holds its previous state when EN is LOW. Asserting both S and R HIGH while EN is HIGH forces both Q and Q_bar outputs to 1. Five signals are shown: EN (enable input), S (set input), R (reset input), and the outputs Q and Q_bar (initially 0 and 1 respectively). Trace Q and Q_bar across all 8 time steps.
Constraints
- Both output signals must be traced for all 8 time steps.
- The latch is level-sensitive and evaluates inputs continuously while the enable signal is HIGH.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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