Gated SR Latch: Output Holds When Enable Drops Mid-State
A gated SR latch updates its output Q according to inputs S and R only while the enable signal EN is HIGH, and holds its last valid state when EN is LOW. Four signals are shown: EN (enable input), S (set input), R (reset input), and Q (output, initially 0). Trace the output Q across all 10 time steps.
Constraints
SandRare never HIGH simultaneously.- The latch is transparent when
ENis HIGH and opaque whenENis LOW.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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