Gated SR Latch: Active-Low Enable
System-level control signals like chip selects, output enables, and bus arbiters frequently use active-low logic to minimize noise sensitivity and default to a safe state. This circuit manages state retention based on an active-low enable signal driven by a controller.
The latch must store the state of the Set (S) and Reset (R) inputs when the output enable (OE_bar) is LOW. When OE_bar is HIGH, the latch must hold its previous value regardless of changes to S and R. Assume S and R will never be HIGH simultaneously.
| OE_bar | S | R | Q (next) | Q_bar (next) | |----------|-----|-----|------------|----------------| | 1 | 0 | 0 | Q | Q_bar | | 1 | 1 | 0 | Q | Q_bar | | 1 | 0 | 1 | Q | Q_bar | | 0 | 0 | 0 | Q | Q_bar | | 0 | 1 | 0 | 1 | 0 | | 0 | 0 | 1 | 0 | 1 |
Constraints
- Construct the core memory element using cross-coupled NOR gates.
- Gate the
SandRinputs using AND gates. - Invert the
OE_barsignal before feeding it to the AND gate enable inputs. - Do not use pre-packaged latch or flip-flop components.
Topics
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