Gated SR Latch: Enable Connected to Wrong NAND Input Debug
A gated SR latch stores a single bit of data and only responds to set and reset inputs when the enable signal is active.
Expected behavior:
| EN | S | R | Q | Q_n | |------|-----|-----|-----|-------| | 1 | 1 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | 1 | | 1 | 0 | 0 | Latch | Latch | | 0 | 0 | 0 | Latch | Latch | | 0 | 1 | 0 | Latch | Latch | | 0 | 0 | 1 | Latch | Latch |
Simulation shows Q changing state when EN=0. Specifically, when transitioning to inputs S=1 and R=0 while EN=0, the output Q incorrectly becomes 1. The latch fails to hold its state and acts as if the enable signal is completely ignored. Inspect the circuit and correct the fault.
Constraints
- Do not add or remove any logic gates.
- Only modify the existing wiring to correct the logic fault.
- Ensure the circuit does not short an output to another output.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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