Gated SR Latch: Enable Gate Addition
Transparent latches sit at the core of static RAM cells and borrow control signals to selectively update state. Gating the inputs allows the latch to hold its value while the enable signal is low, ignoring noise or data changes on the input lines.
Construct a level-sensitive gated SR latch. When the EN signal is high, the circuit must behave as a standard NOR-based SR latch. When EN is low, the latch must hold its previous state regardless of changes to S and R. The circuit remains level-sensitive: it does not wait for a clock edge to update.
| EN | S | R | Q | Qn | |------|-----|-----|-----|------| | 0 | 0 | 0 | Q_old | Qn_old | | 0 | 1 | 0 | Q_old | Qn_old | | 0 | 0 | 1 | Q_old | Qn_old | | 0 | 1 | 1 | Q_old | Qn_old | | 1 | 0 | 0 | Q_old | Qn_old | | 1 | 1 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | 1 | | 1 | 1 | 1 | 0 | 0 |
Constraints
- Implement the core memory element using a cross-coupled NOR gate topology.
- Gate the input signals using AND gates.
- Do not use any edge-triggered flip-flop primitives.
- The circuit must dynamically update
QandQnmultiple times ifSandRchange whileENremains high.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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