D Latch: Construction from Gated SR Latch
Modern digital systems require memory elements that are immune to undefined states. By modifying a basic set-reset structure, designers create data latches that safely store single bits without the risk of an invalid input combination.
Construct a D latch using a provided gated SR latch as the core. The circuit must take a data input D and an enable input EN. When EN is high, the output Q follows D. When EN is low, Q retains its previous state Q_prev. The modification must guarantee that the internal S and R inputs can never be high simultaneously.
| EN | D | Q_prev | Q | |------|-----|----------|-----| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 1 | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | | 1 | 1 | 0 | 1 | | 1 | 1 | 1 | 1 |
Constraints
- Use exactly one NOT gate.
- Connect the
Dinput directly to the internalSterminal. - Connect the inverted
Dsignal to the internalRterminal. - Do not use any additional logic gates.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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