D Latch: 4-NAND Direct Construction
Every master-slave flip-flop relies on area-efficient latch stages to store state. The 4-NAND direct construction is the standard topology for these internal stages, minimizing gate count and propagation delay compared to a discrete logic chain.
Construct a level-sensitive D latch using the absolute minimum number of gates. When EN is high, the outputs Q and Qn track the input D and its complement. When EN is low, the outputs hold their previous state.
| EN | D | Q | Qn | |------|-----|-----|------| | 0 | 0 | Q_prev | Qn_prev | | 0 | 1 | Q_prev | Qn_prev | | 1 | 0 | 0 | 1 | | 1 | 1 | 1 | 0 |
Constraints
- Use exactly 4 NAND gates and 1 NOT gate.
- Do not use an intermediate SR latch block.
- Construct the circuit at the gate level.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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