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Codiode/Problems/Sequential Logic

D Latch: Transparency Window Trace

EasyLogic CircuitTiming Diagram

A positive-level D latch passes its input D directly to the output Q while the enable signal EN is HIGH and holds the last value when EN is LOW. Three signals are shown: EN (enable input), D (data input), and Q (output, initially 0). Trace Q across all 10 time steps.

Constraints

  • Q must match D exactly at any time step where EN is 1.
  • Q must maintain its previous state regardless of D at any time step where EN is 0.

Topics

latchestransparencylevel-sensitive

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