D Latch: Late Glitch Captured at Enable Falling Edge
A D latch passes its input to its output when the enable signal is HIGH and holds its current state when the enable signal is LOW.
Three signals are shown: EN (enable input), D (data input), and Q (output, initially 0).
Trace Q across all 12 time steps.
Constraints
QfollowsDimmediately during any time step whereENis 1.Qretains its last known value whenENtransitions from 1 to 0.- Any changes to
DwhileENis 0 are ignored.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.