SR NOR Latch: Missing Cross-Coupling Wire Debug
An SR NOR latch provides fundamental 1-bit memory storage for sequential state machines.
Expected behavior:
| S | R | Q(t-1) | Q(t) | Q_bar(t) | |-----|-----|----------|--------|------------| | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 1 | 1 | 0 | | 0 | 1 | X | 0 | 1 | | 1 | 0 | X | 1 | 0 |
Simulation shows that driving S=1 and R=0 correctly sets Q=1. However, when transitioning to the hold state S=0 and R=0, Q immediately falls to 0. The circuit fails to hold its state and acts strictly as combinational logic. Inspect the circuit and correct the fault.
Constraints
- The circuit must use exactly two NOR gates.
- The fix must rely entirely on structural routing without adding new logic components.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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