SR NOR Latch: Set-Dominant Configuration
Asynchronous event capture often encounters simultaneous trigger conditions that must be resolved deterministically. The set-dominant latch guarantees a known state during simultaneous assertion of both set and reset signals, eliminating the invalid state of a standard cross-coupled architecture.
Implement a set-dominant SR latch. When S and R are both asserted, the latch must prioritize the set operation and drive Q to 1 and Q_n to 0. All standard latch behaviors must remain intact.
| S | R | Q (next) | Q_n (next) | |-----|-----|------------|--------------| | 0 | 0 | Latch | Latch | | 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 0 | | 1 | 1 | 1 | 0 |
Constraints
- Build the core latch using cross-coupled NOR gates.
- Use standard logic gates to implement the priority masking.
- Do not use pre-packaged flip-flop or latch macro cells.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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