SR NOR Latch: Polarity and Active Level
Power-on reset controllers and fault-handling state machines rely on basic latches to capture transient error events. The SR NOR latch is the fundamental memory element for these systems, but its complementary outputs behave uniquely during simultaneous input assertions.
Implement an SR latch using cross-coupled NOR gates. The circuit must accept a Set (S) and Reset (R) input, driving the primary output Q and its complement Q_bar. Unlike a simple inverter relationship, Q and Q_bar are driven independently. Verify that during the forbidden state when both inputs are asserted, both outputs are driven to logic 0 simultaneously.
| S | R | Q | Q_bar | |-----|-----|-----|---------| | 0 | 0 | Q_prev | Q_bar_prev | | 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 0 | | 1 | 1 | 0 | 0 |
Constraints
- Use exactly two 2-input NOR gates.
- Derive
Q_bardirectly from the NOR gate output, not by invertingQ. - Connect the
Sinput to the NOR gate drivingQ_bar. - Connect the
Rinput to the NOR gate drivingQ.
Topics
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