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Codiode/Problems/Sequential Logic

SR to JK Conversion

HardLogic CircuitBuild

Hardware synthesis tools often map generalized state behaviors to a limited library of standard cells. Implementing toggle functionality on a primitive set/reset cell requires routing the current state back to the inputs to avoid forbidden conditions.

Construct a JK flip-flop using a single SR flip-flop and combinational logic. The circuit must update on the rising edge of clk.

| J | K | Q | Q_next | |-----|-----|-----|----------| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 1 | | 1 | 1 | 0 | 1 | | 1 | 1 | 1 | 0 |

Constraints

  • Use exactly one SR flip-flop.
  • Use basic combinational logic gates to drive the SR flip-flop inputs.
  • Never drive the SR flip-flop's internal set and reset inputs high simultaneously.

Topics

sequential-logicflip-flopsstate-feedback

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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

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