SR Flip-Flop from JK Flip-Flop
Legacy control systems often require strict set/reset semantics where simultaneous assertion is a critical fault. Adapting a universal JK flip-flop to behave as a strict SR flip-flop requires direct input mapping and actively trapping the forbidden state.
The circuit must implement an SR flip-flop using a JK flip-flop as the core state element. The inputs S and R drive the state transitions. Because the SR protocol forbids simultaneous assertion, the condition S=1 and R=1 must be flagged as a violation. The underlying JK flip-flop will naturally toggle in this state, but the overall circuit must output an active-low error flag Err_n to indicate the forbidden configuration.
| S | R | Q_next | Err_n | |-----|-----|----------|---------| | 0 | 0 | Q | 1 | | 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 1 | | 1 | 1 | ~Q | 0 |
Constraints
- Use exactly one JK flip-flop for state retention.
- Drive the
SandRinputs directly into the JK flip-flop without additional combinational steering logic. - Use exactly one NAND gate to monitor the inputs and drive the
Err_nviolation flag. - Do not use any other logic gates.
Topics
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