D-to-JK Conversion
Legacy ASIC migrations frequently require adapting existing standard cell libraries to support new architectural features. The JK flip-flop provides hardware-level toggle functionality, but many modern standard cell libraries provide only D flip-flops.
Design the combinational next-state logic required to convert a standard D flip-flop into a JK flip-flop. The circuit receives the desired J and K control signals along with the current state Q, and must generate the next-state signal D to drive the flip-flop input.
| J | K | Q | D | |-----|-----|-----|-----| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 1 | | 1 | 1 | 0 | 1 | | 1 | 1 | 1 | 0 |
Constraints
- Implement using only combinational logic gates.
- Minimize the total gate count to ensure optimal synthesis.
- Do not use any sequential elements.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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