SRAM Cell Basic Latch
Static random-access memory relies on cross-coupled inverters to hold state without constant refreshing.
The diagram shows a standard 6T SRAM cell core. Two inverters, INV1 and INV2, are connected in a feedback loop to store a single bit at internal nodes Q and Q_bar. Two NMOS access transistors connect these internal nodes to the bitlines BL and BL_bar. The wordline WL controls the gates of both access transistors.
Analyze the feedback loop stability and determine how external signals overdrive the cell during a write operation.
Constraints
- Assume all transistors are ideal switches unless otherwise noted.
WLcontrols the gate of both access transistors simultaneously.- The bitline drivers are assumed to be significantly stronger than the internal inverter pull-up network.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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