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Codiode/Problems/Sequential Logic

Stack Overflow Protection

HardLogic CircuitBuild

Software cannot always be trusted to respect memory boundaries. Hardware stack controllers must defend themselves against invalid operations by interlocking control signals before they reach the memory array.

The protection circuit receives a push command and a full status flag. It generates a safe write_en signal that asserts only when a push is requested and the stack is not full. Additionally, if a push is attempted while the stack is full, an overflow_err flag must assert on the next clock cycle and remain high until synchronously reset.

| rst | push | full | overflow_err (current) | write_en | overflow_err (next) | |-------|--------|--------|--------------------------|------------|-----------------------| | 1 | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 0 | 0 | 0 | 0 | | 0 | 1 | 0 | 0 | 1 | 0 | | 0 | 1 | 1 | 0 | 0 | 1 | | 0 | 0 | 0 | 1 | 0 | 1 | | 0 | 1 | 0 | 1 | 1 | 1 |

Note: The write_en signal must be forced to 0 when rst is active, regardless of other inputs.

Constraints

  • Implement synchronous active-high reset for all sequential elements.
  • Drive write_en using only combinational logic to ensure zero-cycle latency.
  • Use a D flip-flop to store the overflow_err state.

Topics

DatapathInterlockingState Management

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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

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