Simultaneous Push and Pop Resolution
Pipelined processors often encounter structural hazards when a return instruction and a new function call attempt to access the call stack in the same clock cycle. To prevent pipeline stalls, the stack controller must resolve simultaneous push and pop operations gracefully without corrupting the stack pointer.
Design the pointer and write-enable logic for a synchronous stack controller. The circuit maintains a 4-bit stack pointer ptr that tracks the current top of the stack. When a simultaneous push and pop occurs, the pointer must not change, but the new push_data must immediately overwrite the data being popped at the current pointer address.
| push | pop | ptr (next cycle) | we | waddr | wdata | |--------|-------|--------------------|------|---------|---------| | 0 | 0 | ptr | 0 | 0 | 0 | | 1 | 0 | ptr + 1 | 1 | ptr + 1 | push_data | | 0 | 1 | ptr - 1 | 0 | 0 | 0 | | 1 | 1 | ptr | 1 | ptr | push_data |
Constraints
- Implement
ptras a 4-bit register initialized to 0 on a synchronous active-highrst. - Output 0 for both 4-bit
waddrand 8-bitwdatawheneverweis 0. - Generate control signals for an external RAM rather than instantiating internal memory blocks.
Topics
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