Synchronous 3-bit Binary Counter with Reset
A synchronous counter is preferred over a ripple counter in all timing-critical designs because every flip-flop is driven by the same clock — there is no ripple delay, and the counter state is valid and stable at every clock edge. Synchronous counters are used in baud rate generators, PWM period controllers, state machine cycle timers, and address sequencers. Every digital design interview includes at least one synchronous counter question.
Your task is to implement a 3-bit synchronous binary counter with a synchronous active-high reset. When RST=1 on a clock edge, the counter loads 000. When RST=0, the counter increments by 1 on each positive clock edge, counting 000 → 001 → 010 → 011 → 100 → 101 → 110 → 111 → 000 (wrap around).
The excitation equations for a synchronous counter using D flip-flops: Q0 toggles every cycle: D0 = NOT(Q0) when RST=0, D0 = 0 when RST=1. Q1 toggles when Q0=1: D1 = Q1 XOR Q0 when RST=0, D1 = 0 when RST=1. Q2 toggles when Q0=1 AND Q1=1: D2 = Q2 XOR (Q0 AND Q1) when RST=0, D2 = 0 when RST=1. Reset is implemented by routing each D through a MUX: D_i = RST ? 0 : excitation_i.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | CLK | input | 1 | Clock, positive-edge triggered | | RST | input | 1 | Synchronous active-high reset: forces count to 000 on next clock edge | | Q2 | output | 1 | MSB of the 3-bit count | | Q1 | output | 1 | Middle bit of the count | | Q0 | output | 1 | LSB of the count |
Constraints
- All three DFF inputs must be driven by the same CLK — this is a synchronous design.
- RST is synchronous: the counter resets to 000 on the first positive clock edge after RST is asserted. It does not reset immediately.
- The optimal 10-component solution uses 1 NOT, 1 XOR, 1 AND, 1 XOR, and 3 MUX components (for the RST steering), plus 3 DFF components.
- When RST=0 and the counter is at 111, the next state on the next clock edge must be 000.
Topics
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