Synchronous Counter: Decoded Output Glitches
A combinational decoder DEC outputs 1 when the counter state Q3 Q2 Q1 Q0 is 1000, while a positive-edge-triggered register REG_DEC captures DEC at every LOW-to-HIGH transition of CLK.
Seven signals are shown: CLK (clock, period 2), Q3, Q2, Q1, and Q0 (counter bits, undefined X during the t_pcq transition window), DEC (combinational output), and REG_DEC (registered output, initially 0).
Trace DEC and REG_DEC across all 12 time steps.
Constraints
DECis purely combinational and evaluates immediately based on the currentQbits.REG_DECcaptures the value ofDECpresent exactly at the setup window before the rising edge ofCLK.- Any operation involving an undefined input
Xresults in an undefined outputX.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.