Synchronous Counter with Enable
A 2-bit synchronous up-counter increments its value on the rising edge of the clock only when the enable signal is high.
Four signals are shown: CLK (clock, period 2), EN (input), Q0 (output LSB), and Q1 (output MSB). Both output bits are initially 0.
Trace Q0 and Q1 across all 14 time steps.
Constraints
- The counter only updates its state on the LOW-to-HIGH transition of
CLK. - When
ENis LOW during a rising clock edge, the counter holds its current value.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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