4-Bit Synchronous Counter Using JK Flip-Flops
Legacy discrete logic families like the 74LS191 rely heavily on JK flip-flops to implement counting and state machine functions. Mastering JK excitation logic is essential for analyzing older schematics and understanding the foundation of synchronous counter design.
Construct a 4-bit synchronous up-counter using JK flip-flops. On every rising edge of clk, the 4-bit output formed by Q3, Q2, Q1, and Q0 must increment by 1. When the counter reaches 15 (1111), it must wrap around to 0 (0000). An active-high asynchronous rst signal must clear all outputs to 0 immediately when asserted.
Use the standard JK flip-flop excitation table to derive the logic for each stage:
| Q(t) | Q(t+1) | J | K | |--------|----------|-----|-----| | 0 | 0 | 0 | X | | 0 | 1 | 1 | X | | 1 | 0 | X | 1 | | 1 | 1 | X | 0 |
Constraints
- Use exactly four JK flip-flops.
- Connect the
rstinput to the asynchronous clear ports of all flip-flops. - Derive and implement the combinational logic for the
JandKinputs using only AND gates. - Do not use D flip-flops, T flip-flops, or pre-built counter modules.
Topics
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