Synchronous Counter Q3 Stuck-at-0 Debug
A 4-bit synchronous up counter tracks clock pulses and increments its binary value on every active clock edge. The circuit should count from 0 to 15 and then wrap around to 0.
Expected behavior:
| State | Q3 | Q2 | Q1 | Q0 | |-------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | 1 | | 2 | 0 | 0 | 1 | 0 | | 3 | 0 | 0 | 1 | 1 | | 4 | 0 | 1 | 0 | 0 | | 5 | 0 | 1 | 0 | 1 | | 6 | 0 | 1 | 1 | 0 | | 7 | 0 | 1 | 1 | 1 | | 8 | 1 | 0 | 0 | 0 | | ... | ... | ... | ... | ... | | 15 | 1 | 1 | 1 | 1 |
Simulation shows the counter advancing from state 0 to state 7 correctly. On the next clock pulse, the circuit outputs Q3=0, Q2=0, Q1=0, Q0=0 instead of state 8. The Q3 output remains 0 for all states in an infinite cycle.
Inspect the circuit and correct the fault.
Constraints
- Do not alter the clock distribution network.
- Preserve the synchronous architecture: all flip-flops must be driven by the same clock signal.
- Use only standard logic gates for the next-state logic.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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