T Flip-Flop: 2-Bit Binary Ripple Counter Wiring
Hardware timers and frequency dividers rely on cascaded flip-flops to track state transitions over time. The 2-bit binary counter forms the foundation of these timing circuits by sequentially advancing through four distinct states.
The circuit must produce a 2-bit binary count (Q1, Q0) that increments on each clock cycle. Q0 represents the least significant bit and toggles on every active edge. Q1 represents the most significant bit and toggles only when Q0 is high. An active-high rst signal must synchronously clear both outputs to 0.
| rst | Current Q1 | Current Q0 | Next Q1 | Next Q0 | |-------|--------------|--------------|-----------|-----------| | 1 | X | X | 0 | 0 | | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 1 | 1 | | 0 | 1 | 1 | 0 | 0 |
Constraints
- Use exactly two T flip-flops.
- Drive both flip-flops with the same global clock signal to ensure synchronous operation.
- Tie the T input of the first stage to a constant logic high.
- Wire the T input of the second stage directly to the
Q0output.
Topics
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