T Flip-Flop: Which T Value Is Captured When T Changes at the Clock Edge
A positive-edge-triggered T flip-flop toggles its output state if the input T is 1 immediately prior to the rising edge of the clock.
Three signals are shown on the logic analyzer trace. CLK is the clock signal with a period of 2. T is the toggle input. Q is the flip-flop output and initializes to 0.
Trace the output signal Q across all 10 time steps.
Constraints
- Output
Qonly updates on the LOW-to-HIGH transition ofCLK. - If
Ttransitions at the exact same time step as the clock edge, the flip-flop captures the pre-edge value from the previous time step.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.