CodiodeCodiode
Home
Problem Solving
Skill Tracks
My Assignments
Contests
Leaderboard
Community
Settings
Codiode/Problems/Sequential Logic

T Flip-Flop Conversion to JK

HardLogic CircuitBuild

Universal flip-flop conversions are foundational for legacy ASIC migrations and standard cell library optimizations. A JK flip-flop provides explicit set, reset, and toggle capabilities without the forbidden state of an SR latch.

Implement a JK flip-flop using exactly one T flip-flop and standard combinational logic gates. The circuit must evaluate the inputs J and K alongside the current state Q to determine the correct toggle signal for the underlying T flip-flop.

| J | K | Q_next | |-----|-----|----------| | 0 | 0 | Q | | 0 | 1 | 0 | | 1 | 0 | 1 | | 1 | 1 | ~Q |

Constraints

  • Use exactly one T flip-flop.
  • Use only AND, OR, and NOT gates for the input logic network.
  • Do not use any additional sequential elements or latches.

Topics

flip-flopsstate-feedbacklogic-conversion

Solve this problem

Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

This problem is part of Codiode Pro. The statement above is free to read.

Sign in to solveSee what Pro unlocks

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Related problems

  • 3-bit Ripple Counter from Toggle Flip-FlopsEasy
  • D Latch from a 2:1 MUXEasy
  • 2-bit Ring CounterEasy
  • T Flip-Flop from a D Flip-FlopEasy
  • Handshake Deadlock Due to Early ResetHard
  • Reconvergence of Individually Synchronized BitsHard
  • Debug: Asynchronous Clear GlitchHard
  • Clock Gate Enable Crossing DomainsHard

Browse all problems · Learning tracks