T Flip-Flop: Divide-by-3 Counter Design
Clock dividers in communication systems often require non-power-of-two ratios to generate specific baud rates or timing signals. A divide-by-3 counter provides a fundamental building block for these custom frequency synthesizers.
The circuit must sequence through the states 00, 01, and 10 on each rising edge of clk. If the circuit enters the invalid state 11 due to a glitch, it must recover by transitioning back to 00 on the next clock edge.
| Current Q1 | Current Q0 | Next Q1 | Next Q0 | |--------------|--------------|-----------|-----------| | 0 | 0 | 0 | 1 | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 0 | | 1 | 1 | 0 | 0 |
Constraints
- Use exactly two T flip-flops.
- Implement combinational logic to derive the T inputs from the current state.
- Ensure the invalid state 11 unconditionally transitions to 00 on the next clock edge.
Topics
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