Triple Flip Flop Synchronizer
High-speed clock domains reduce the available time for metastable signals to resolve before the next clock edge. Increasing the mean time between failures (MTBF) in these extreme frequency environments requires extending the synchronization pipeline beyond the standard two stages.
Route the asynchronous input async_in through a three-stage flip-flop synchronizer. Connect the final synchronized output to sync_out. To monitor the node with the highest probability of unresolved metastability, route the output of the first synchronization stage to meta_probe.
Constraints
- Use exactly three D-type flip-flops.
- Connect all flip-flop clock pins to the single implicit clock domain.
- Do not insert combinational logic between the synchronization stages.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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