Standard Dual Flip Flop Synchronizer
Every asynchronous signal entering a digital system must be synchronized to the local clock domain to prevent metastability from propagating. The dual flip-flop synchronizer is the standard primitive for safely crossing single-bit control signals into a new clock domain.
The circuit captures the incoming async_in signal and delays it by two clock cycles of the destination clock clk. An active-low asynchronous reset rst_n clears all internal state immediately.
| rst_n | clk | async_in | Internal Stage | sync_out | |---------|-------|------------|----------------|------------| | 0 | X | X | 0 | 0 | | 1 | ↑ | 0 | 0 | Previous Internal | | 1 | ↑ | 1 | 1 | Previous Internal | | 1 | 0/1 | X | No Change | No Change |
Constraints
- Use exactly two D flip-flops.
- Connect the destination clock
clkdirectly to the clock pins of both flip-flops. - Route the active-low reset
rst_ndirectly to the asynchronous reset pins of both flip-flops. - Do not place any combinational logic between the two flip-flop stages.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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