Metastable Window Identification
A positive-edge-triggered D flip-flop captures the value of D at every LOW-to-HIGH transition of CLK unless a setup or hold time violation occurs. Three signals are shown: CLK (clock, period 2), D (asynchronous input) and Q (output, initially 0). If D transitions on the exact same time step as the rising edge of CLK, the flip-flop enters a metastable state where the output voltage is indeterminate. Trace Q across all 8 time steps, using X for any time step where the output is metastable.
Constraints
- Use the exact string
"X"to represent an indeterminate or metastable state. - A metastable state persists until a valid, stable input is captured on a subsequent clock edge.
- The initial value of
Qat time step 0 is 0.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.