Missing Clock Watchdog Timer
Mission-critical systems cannot freeze when a primary oscillator fails. A watchdog circuit monitors the primary high-speed clock using a reliable low-speed reference clock, automatically triggering a failover sequence or system reset if the primary clock dies.
The circuit must monitor clk_fast using clk_slow. Assert alarm high if no rising edges are detected on clk_fast for three consecutive rising edges of clk_slow. If a rising edge occurs on clk_fast, the internal monitor must reset. The system is initialized with an active-low asynchronous reset rst_n.
Constraints
- Implement using only standard combinational logic gates and D flip-flops.
- The
alarmoutput must be synchronous toclk_slow. - Do not use high-level behavioral counter blocks.
- Handle asynchronous clock domains safely to prevent metastability.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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