Frequency Comparator
Fault-tolerant systems must continuously monitor primary oscillators to detect if a clock has failed or drifted out of specification. A frequency comparator measures two asynchronous clock domains against each other to determine which is running faster.
The circuit receives two independent clocks, clk_a and clk_b, and an active-high reset rst. When rst is deasserted, the circuit must count the edges of both clocks over a fixed measurement window. The window is defined by exactly 4 cycles of clk_a.
Once the 4-cycle window completes, the circuit must assert done to 1. If clk_a had more cycles than clk_b during this period, assert a_faster to 1 and b_faster to 0. If clk_b had more cycles, assert b_faster to 1 and a_faster to 0. If the counts are equal, both are 0. The outputs must remain stable until the next reset.
Constraints
- Implement independent edge counters in both the
clk_aandclk_bdomains. - Use a synchronization protocol to cross domain boundaries for the comparison.
- Do not use combinational logic to directly compare the raw clock signals.
- All outputs must be glitch-free and registered.
Topics
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