Three Way Glitch Free Multiplexer
Modern processors dynamically switch between high-performance, efficiency, and ultra-low-power oscillators to optimize the power-performance envelope. Scaling clock multiplexing beyond two sources requires careful cascading to prevent runt pulses or glitches during the transition.
The circuit must select one of three asynchronous clock sources (clk0, clk1, clk2) based on a 2-bit selection signal (sel1, sel0) and route it to clk_out. The transition between any two clocks must be completely glitch-free.
| sel1 | sel0 | Active Clock | |--------|--------|--------------| | 0 | 0 | clk0 | | 0 | 1 | clk1 | | 1 | 0 | clk2 | | 1 | 1 | 0 |
Constraints
- Cascade two 2-to-1 glitch-free clock multiplexers to form the 3-way multiplexer.
- Use negative-edge triggered flip-flops for all clock synchronization stages.
- Design the select decoding logic so that intermediate clock lines never glitch during a
sel1orsel0transition. - Ensure
clk_outremains strictly at 0 whensel1andsel0are both 1.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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