Clock Switch with Asynchronous Reset
A glitch-free clock multiplexer must power up in a deterministic state to ensure downstream logic receives a valid clock immediately. If the synchronization flip-flops initialize randomly, the entire chip may receive no clock and fail to boot.
Implement a glitch-free clock switch that selects between clk_a and clk_b based on the sel signal. To prevent runt pulses during switching, use negative-edge-triggered synchronizers with cross-coupled feedback to enforce a break-before-make policy. The circuit must use the active-high asynchronous rst signal to force the switch into a safe state where clk_a is selected by default.
| rst | sel | Active Clock | clk_out | |-------|-------|--------------|-----------| | 1 | X | clk_a | clk_a | | 0 | 0 | clk_a | clk_a | | 0 | 1 | clk_b | clk_b |
Constraints
- Implement a break-before-make glitch-free clock multiplexer.
- Use only negative-edge-triggered flip-flops for synchronization.
- Route the asynchronous
rstsignal to the flip-flop preset and clear pins to enforceclk_aas the default. - Do not use positive-edge-triggered flip-flops.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.